BERKELEY, CA—(Marketwired – March 10, 2017) – Over the last year the RISC–V architecture has evolved from an academic research interest to a mainstream embedded processor technology with a rich ecosystem and a fast–growing number of real–world implementations. As a sign of this progress, a number of companies will be demonstrating commercial implementations of RISC–V products next week at Embedded World 2017, the leading international trade fair for embedded systems (March 14–16, Nuremberg, Germany) https://www.embedded–world.de/en.
RISC–V is an open processor Instruction Set Architecture (ISA) that is maintained by the RISC–V Foundation (https://riscv.org), and offers an open alternative to the traditional devices used in embedded products today. The Linley Group selected RISC–V as its “Technology of the Year” for 2016.
“More than just a processor ISA, RISC–V is building a rich ecosystem to include system–IP, development systems and software implementations,” said Rick O'Connor, Executive Director of the RISC–V Foundation. “It is a sign of the growing maturity of that ecosystem to have some of our member companies, with very different business models and product strategies, demonstrating commercial implementations of RISC–V at Embedded World.”
- Microsemi (Hall 1, Booth 1–660) will be demonstrating RISC–V–based FPGA solutions, available for customers to adopt and incorporate into their designs. In addition, it will be hosting regular RISC–V seminars at its booth, highlighting the benefits of moving from a proprietary ISA to an open ISA. Sign up for a session at https://www.microsemi.com/industry–events/embedded–world–2017/.
“As early promoters of the RISC–V standard we have been excited to see how quickly it has grown and been accepted by the wider designing community,” said Ted Marena, director of FPGA marketing at Microsemi. “At Embedded World we will be demonstrating our E31 RISC–V IP core running on our FPGAs and provide insight into our future plans based on the unique capabilities of RISC–V.”
- Codasip (Hall 3, Booth 3–627) will be demonstrating their Codix–Bk series of RISC–V embedded processors IP for SoC designs. The benefits of RISC–V extensibility will also be shown with security extensions from partner SecureRF.
“RISC–V is now the primary driver of our embedded IP roadmap,” said Karel Masarik, CEO Codasip. “The power of the RISC–V solution is that customers not only benefit from our extremely flexible IP implementations, but can leverage the rich software ecosystem that is already building. Together with our partners, we are excited to be demonstrating our latest RISC–V compliant products at Embedded World.”
- UltraSoC (Hall 3, Booth 3–555) will be demonstrating their powerful SoC Analysis and Debug infrastructure that includes native RISC–V processor IP support.
“We're delighted to be able to support RISC–V, and to demonstrate how strong the ecosystem of commercially available supporting IP now is,” said Rupert Baines, UltraSoC CEO. “Our stance is vendor neutral and ecosystem based. We aim to create a universal development infrastructure in which designers can freely choose the best architecture for the job, to create uniquely differentiated products. I believe our approach is an excellent fit with the aims and aspirations of the RISC–V movement.”
- Antmicro (Hall 4A, Booth 4A–121) will be demonstrating a RISC–V (SiFive FE310) based System on Module with a matching baseboard, their AXIOM Gamma 4K camera with soft RISC–V IP inside, as well as 2D graphics IP that can be used to build custom silicon with good–looking, low power User Interfaces.
“The proven and now industry accepted standard RISC–V ISA paves the way for software–driven silicon that answers the needs of modern programming paradigms and reflects the open ecosystem of tooling that has allowed the industry to flourish,” said Michael Gielda, Business Development Manager at Antmicro. “RISC–V does to embedded design what the rich open standards have done for web design, generating new use cases and business opportunities. Our module, software and IP are meant to be vehicles driving early RISC–V applications.”
For those unable to visit Embedded World, the RISC–V Foundation website (riscv.org) includes a rich set of information to help both those new to the RISC–V standard, and those looking to dive deeper.
The RISC–V Workshop presentations highlight just a few of the (https://riscv.org/workshops/) achievements of our member companies, and for even more in–depth RISC–V experience we invite you to attend one of the workshops in person.
About the RISC–V Foundation
RISC–V (pronounced “risk–five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC–V Foundation. The RISC–V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.
The RISC–V Foundation, a non–profit corporation controlled by its members, directs the future development and drives the adoption of the RISC–V ISA. Members of the RISC–V Foundation have access to and participate in the development of the RISC–V ISA specifications and related HW / SW ecosystem.